SCF2015 Workshops offer attendees a variety of short courses on key topics and technologies relevant to high performance computing, programming, debugging & novel architectures. These workshops also provide the opportunity to interact with recognized leaders in the field and to learn about the latest technology trends, theory, and practical techniques.
Our workshops are open to all conference attendees except those who are on 1-Day passes but registrations for the workshops are required. For those of you who are only interested in attending the workshops but not the conference from 17 – 19 March 2015, we have introduced a special workshop-only fee of SG$100. Please check out the details on our registration page.
Please note:
The conference workshops will be held on Friday, 20 March 2015.
Monte Carlo Methods and High-Performance Computing
Time:
9:00am – 5:00pm
Venue:
Level 4, Matrix Building, Biopolis
Breaks:
Morning & afternoon tea breaks and lunch
Presenter:
Michael Mascagni, Florida State University & National Institute of Standards and Technology, USA
Abstract:
The modern development of Monte Carlo methods (MCMs) coincides with the modern development of digital computation and high-performance computing (HPC). This was due to the intrinsic ease of implementation and execution of MCMs on HPC platforms. This close relationship persisted through the introduction of multiple processing elements, vectorizing hardware, Single Instruction Multiple Data (SIMD) hardware, Multiple Instruction Multiple Data (MIMD) and into the modern architectural era with multicore hardware and hybrid architectures that include GPGPUs. This course introduces the students to modern MCMs, which are now essential in many fields, including nanomaterials, financial engineering, computational physics, structural biology, and scientific computing. The algorithmic presentation stresses ways of identifying and exploiting the ample parallelism in these naturally parallel numerical techniques. In addition, an overview of modern HPC hardware and future trends in HPC is presented, and this material is likewise filtered through MCM implementation.
Micron’s Automata Processor: A Massively Parallel Computing Solution
Time:
9:00am – 3:00pm
Venue:
Level 4, Matrix Building, Biopolis
Breaks:
Morning tea break and lunch
Presenter:
Terry Leslie, Director of Business Development, Automata Processing Team, Micron Technology
Matt Tanner, Senior Applications Engineer, Advanced Computing Solutions Group, Micron Technology
Abstract:
Many of today’s most challenging computer science problems – such as those involving very large data structures, unstructured data, random access or real-time performance requirements – require highly parallel solutions. The current implementation of parallelism can be cumbersome and complex, challenging the capabilities of traditional CPU and memory system architectures and often requiring significant effort on the part of programmers and system designers.
For the past seven years, Micron Technology has been developing a hardware co-processor technology that can directly implement large-scale Non-deterministic Finite Automata (NFA) for efficient parallel execution. This new non-Von Neumann processor, currently in fabrication, borrows from the architecture of memory systems to achieve massive data parallelism, addressing complex problems in an efficient, manageable method.
This workshop will provide an overview on this revolutionary new technology, the growing ecosystem, as well as potential applications such as bioinformatics, video and image analysis and cyber security.
An Introduction to Xeon Phi programming and sharing a Numerical Library developer’s experience using the Xeon and Xeon Phi.
Time:
9:00am – 1:00pm
Venue:
Level 4, Matrix Building, Biopolis
Breaks:
Morning tea break and lunch
Presenter:
Brian Spector, Technical Consultant, The Numerical Algorithms Group (NAG)
Abstract:
This 1/2 day workshop introduces parallel program development for the Intel Xeon Phi coprocessor using basic OpenMP. It will discuss the architecture of the system and teach an introduction to developing parallel applications (with OpenMP) targeting the Xeon Phi using both its native and offload modes of execution.
We start by introducing the basics of x86 architecture and extending this description into more specific details of the Intel Xeon Phi architecture. We then present some of the basics of OpenMP and Intel’s Language Extensions for Offload (LEO) — Intel’s compiler directives for using the Xeon Phi alongside the host system. Important topics discussed include data offloading, code profilers, and vectorization. Finally, we demonstrate using the NAG SMP Library for Xeon Phi and show examples of performance gains and pitfalls while coding on the Phi.
Application Programming for Efficiency on Parallel Supercomputers
Time:
9:00am – 5:00pm
Venue:
Level 4, Matrix Building, Biopolis
Breaks:
Morning & afternoon tea breaks and lunch
Presenter:
Zaphiris Christidis, Senior IT Architect, Lenovo Inc.
Abstract:
This workshop includes a tutorial in efficient FORTRAN programming on XEON processors. Various single core optimization techniques in programming are examined and several examples are presented. In turn, principles of shared memory programming using OpenMP, and distributed memory programming using MPI are described and several examples from real application programs are given.
From High Performance Computing to High Efficiency Computing with Allinea
Time:
9:00am – 1:00pm
Venue:
Level 4, Matrix Building, Biopolis
Breaks:
Morning tea break and lunch
Presenter:
Patrick Wohlschlegel, Technical Services Manager, Allinea
Abstract:
Allinea is an HPC software tools company whose tools are widely used in the biggest supercomputing centers worldwide, including A*STAR. Allinea endeavors to help scientists resolve challenging issues at all stages in their applications life-cycle. In the development stage, Allinea Forge – the well established development environment that includes Allinea DDT and Allinea MAP – provides unique capabilities to help debug and optimize HPC applications. Later during production, Allinea Performance Reports has proved to be invaluable to understand complex workloads and increase the efficiency of Supercomputers.
During this hands-on workshop, Allinea will provide you with an introduction to Allinea Forge and Allinea Performance Reports. Through various exercises, we will see how to develop and run high quality and efficient codes.
GPU Programming Workshop with Use Cases in Deep Learning, IVA and Autonomous Driving
Time:
9:00am – 5:00pm
Venue:
Level 4, Matrix Building, Biopolis
Breaks:
Morning & afternoon tea breaks and lunch
Presenter:
Sanjiv Satoor, CUDA Performance Analysis Tools Manager, NVIDIA
Abstract:
The GPU has propelled computer graphics from a feature into an ever-expanding industry — encompassing scientific research, supercomputing, and product design among many other categories. GPUs are now driving new fields like deep learning (the use of sophisticated, multi-level “deep” neural networks to create systems that can perform feature detection from massive amounts of unlabeled training data), computer vision, image processing and augmented reality.
This workshop will show how other scientists and industry professionals are advancing their work in the field of machine learning, Intelligent Video Analytics (IVA), autonomous driving, and provide information about GPU programming tools, software frameworks, and computing configurations that will help you get started.
Sanjiv will discuss where GPU acceleration fits in the context of deep learning, IVA and autonomous driving use cases. He will cover what’s latest in hardware and software, GPU and CUDA roadmap, and how to get started with GPU programming. Workshop will feature hands-on GPU programming session (laptop and headphones are required for this course).